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rev 1.8, march 16 , 2012 page 1 of 12 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com SL18860DC key features ? l ow current consumption - 2.7 ma- typ (vdd=1.8v and cl=0) ? 1.7 v to 3. 6 5 v power supply operation ? 10mhz to 52mhz clkin ? supports lvcmos and clipped sine wave inputs ? s uports 3 s ingle - ended lv cmo s square wave outputs ? oe 1/2/3 f unction s for each clkout1/2/3 outputs ? oe_osc control pin to enable external tcxo/xo ? ultra - low phase noise ? ultra low standby current ? 10- pin tdfn package (1.4x2.0x0.75 mm) ? industrial -40 oc to 85 oc temperature range application ? sm art mobile handsets ? multi - mode rf clock distribution ? baseband peripheral clock distribution description the SL18860DC product is a high performance 3 output clock distribution buffer and provides 3 outputs from a single input clock b y using sli proprietary low phase noise and low power dissipation circuit design . the SL18860DC can be used in baseband mobile rf applications including wlan , bluetooth and dvb - h as an input clock reference. the product designed to isolate each device driven by their clock outputs to minimize interference between these devices. each of the clock buffer outputs can be individually di sabled by using oe1/2/3 control pins to reduce the power consumption if the connected device does not need the clock. the device operates from single power supply from 1.7v to 3.65 v and from -40 oc to 85 oc . benefits ? fast t ime -to -m arket ? cost reduction ? low power dissipation ? low phase noise block diagram control logic 6 7 5 10 4 8 9 3 2 1 clkout1 clkout2 clkout3 clkin vdd vss oe2 oe3 oe1 oe_osc 3 - channel clock distribution buffer
rev 1.8, march 16 , 2012 page 2 of 12 SL18860DC pin configuration 10 9 8 7 1 2 3 4 clkout3 clkout2 clkout1 oe2 vss vdd clkin oe_osc oe3 5 6 oe1 10- pin tdfn package pinout pin description pin number pin name pin type pin description 1 vss power power supply ground. 2 vdd power 2.25 to 3.65v or 1.8v +/ - 5% positive power supply 3 clkin input external clock input pin. vss to vdd cmos level. 4 oe_osc output crystal oscillator enable pin. if oe1=oe2=oe3=0 then oe_osc=0. oe_osc=1 for all the other oe1/2/3 logic states. 5 oe3 input output enable pin for clkout3. the input has 150k ? - typ on - chip pull - down resistor. 6 oe1 input output enable pin for clkout1. the input has 150k ? - typ on - chip pull - down resistor. 7 oe2 input output enable pin for clkout2. the input has 150k ? - typ on - chip pull - down resistor. 8 clkout1 output clock output - 1. clock frequency is the same as clkin. 9 clkout2 output clock output - 2. clock frequency is the same as clkin. 10 clkout3 output clock output - 3. clock frequency is the same as clkin. table 1. truth table for oe1/2/3, oe_osc and clkout1/2/3 oe1 (input) oe2 (input) oe3 (input) oe_osc (output) clkout1 clkout2 clkout3 0 0 0 0 hi - z hi - z hi - z 1 0 0 1 clock hi - z hi - z 1 1 0 1 clock clock hi - z ? ? ? ? ? ? ? 1 1 1 1 clock clock clock
rev 1.8, march 16 , 2012 page 3 of 12 SL18860DC absolute ma ximum ratings description condition min max unit supply voltage, vd d (absolute) - 0.5 4.6 v supply voltage, vd d (operation) 1.70 3.65 v all inputs and outputs - 0.5 vdd+0.5 v ambient operating temperature in operation, c - grade -40 85 c storage temperature no power is applied -65 150 c junction temperature in operation, power is applied - 125 c soldering temperature - 260 c esd rating (human body model) jedec22 - a114d - 4,000 4,000 v esd rating (charge device model) jedec22 - c101c - 1,500 1,500 v esd rating (machine model) jedec22 - a115d -200 200 v dc electrical characteristics (i - grade) unless otherwise stated vdd= 1.8 v +/ - 5% and operation temperature range - 40 to +85 c description symbol condition min typ max unit operating voltage vdd operation range , 1.8v+/ -5% 1.7 0 1.80 1.90 v operating temperature ta i - grade -40 25 85 oc input low voltage vil cmos level, pins 3, 5, 6 and 7 vss - 0. 3vdd v input high voltage vih cmos level, pins 3 , 5, 6 and 7 0.7vdd - vdd v output high voltage voh ioh= -4 ma , pins 4, 8, 9 and 10 vdd - 0.4 - - v output low voltage vol iol= -4 ma, pins 4, 8, 9 and 10 - - 0.4 v input leakage current ilh vin=vdd, pins 5, 6 and 7 -25 - 25 a input leakage current ill vin=gnd, pins 5, 6 and 7 -10 - 10 a pull -do wn resistor rp d pins 5, 6 and 7 100 150 250 k operating supply current idd1 clkin=26mhz, oe1=oe2=oe3=1 - 2.7 - ma operating supply current idd2 oe1=oe2=oe3=0 clkin=low or high - - 1.0 a input capacitance cin pins 5, 6 and 7 - 3 5 pf load capacitance cl clkout 1/2/3, pins 8, 9 and 10 - 10 20 pf
rev 1.8, march 16 , 2012 page 4 of 12 SL18860DC ac electrical characteristics (i - grade) unless otherwise st ated vdd= 1.8v+/ - 5% and operation temperature range - 40 to +85c parameter symbol condition min typ max unit input clock range clkin external clock, cmos square wave 10 26.000 52 mhz output clock range clkout external clock, cmos square wave clkout1/2/3 10 26.000 52 mhz input clock voltage swing level vinpp vdd=1.8v 0.7 2 1 - vpp input duty cycle dcin clkin, pin 3 30 50 70 % output clock rise time tr vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 2.0 4.00 ns output clock fall time tf vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 2.0 4.00 ns additive phase noise apn -1 clkin=26mhz and 1 khz offset clkout1/2/3 - -140 - dbc/hz additive phase noise apn -2 clkin=26mhz and 10 khz offset clkout1/2/3 - -1 50 - dbc/hz additive phase noise apn -3 clkin=26mhz and 100 khz offset clkout1/2/3 - -159 - dbc/hz power - up time tpu time duration until clkout1/2/3 fr equency reaches valid frequency after power supply reaches 0.9xvdd value - 100 2 00 n s output enable time toe1 time from oe raising edge to active at outputs clkout1/2/3 (asynchronous) - 25 - n s output disable time tod time from oe falling edge to hi - z at outputs clkout1/2/3 (asynchronous) - 25 - n s output enable time toe2 active recovery time from standby (clkin=0 or 1) to active at outputs clkout1/2/3 - 100 - n s
rev 1.8, march 16 , 2012 page 1 of 12 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com SL18860DC dc electrical characteristics (i - grade) unless otherwise stated vdd= 2.5 v +/ - 10 % and operation temperature range - 40 to +85c description symbol condition min typ max unit operating voltage vdd operation range , 2.5v+/ -10% 2.25 2.50 2.75 v operating temperature ta i - grade -40 25 85 oc input low voltage vil cmos level, pins 3, 5, 6 and 7 vss - 0. 3vdd v input high voltage vih cmos level, pins 3, 5, 6 and 7 0.7vdd - vdd v output high voltage voh ioh= -4 ma , pins 4, 8, 9 and 10 vdd - 0.4 - - v output low voltage vol iol= -4 ma, pins 4, 8, 9 and 10 - - 0.4 v input leakage current ilh vin=vdd, pins 5, 6 and 7 -30 - 30 a input leakage current ill vin=gnd, pins 5, 6 and 7 -1 5 - 1 5 a pull -do wn resistor rp d pins 5, 6 and 7 100 150 250 k operating supply current idd1 clkin=26mhz, oe1=oe2=oe3=1 - 3.0 - ma operating supply current idd2 oe1=oe2=oe3=0 clkin=low or high - - 1. 5 a input capacitance cin pins 5, 6 and 7 - 3 5 pf load capacitance cl clkout 1/2/3, pins 8, 9 and 10 - 10 20 pf ac electrical characteristics (i - grade) unless otherwise st ated vdd= 2.5v+/ - 10 % and operation temperature range - 40 to +85c parameter symbol condition min typ max unit input clock range clkin external clock, cmos square wave 10 26.000 52 mhz output clock range clkout external clock, cmos square wave clkout1/2/3 10 26.000 52 mhz input clock voltage swing level vinpp vdd=2.5v, connect to clkin directly 1.0 1.2 - v vdd=2.5v, connect to clkin through ac coupling and bias circuit 0.6 - - v input duty cycle dcin clkin, pin 3 30 50 70 % output clock rise time tr vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 2.0 4.00 ns output clock fall time tf vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 2.0 4.00 ns additive phase noise apn -1 clkin=26mhz and 1 khz offset clkout1/2/3 - -142 - dbc/hz
rev 1.8, march 16 , 2012 page 2 of 12 SL18860DC additive phase noise apn -2 clkin=26mhz and 10 khz offset clkout1/2/3 - -1 5 6 - dbc/hz additive phase noise apn -3 clkin=26mhz and 100 khz offset clkout1/2/3 - -164 - dbc/hz power - up time tpu time for clkout1/2/3 fr equency to reach valid frequency after power supply reaches 0.9xvddvalue - 100 200 n s output enable time toe1 time from oe raising edge to active at outputs clkout1/2/3 (asynchronous) - 25 - n s output disable time tod time from oe falling edge to hi - z at outputs clkout1/2/3 (asynchronous) - 25 - n s output enable time toe2 active recovery time from standby (clkin=0 or 1) to active at outputs clkout1/2/3 - 100 - n s dc electrical characteristics (i - grade) unless otherwise stated vdd= 3.3 v +/ - 10 % and operation temperature range - 40 to +85c description symbol condition min typ max unit operating voltage vdd operation range , 3.3v+/ -10% 2.95 3.3 3.65 v operating temperature ta i - grade -40 25 85 oc input low voltage vil cmos level, pins 3. 5, 6 and 7 vss - 0. 3vdd v input high voltage vih cmos level, pins 3. 5, 6 and 7 0.7vdd - vdd v output high voltage voh ioh= -4 ma , pins 4, 8, 9 and 10 vdd - 0.4 - - v output low voltage vol iol= -4 ma, pins 4, 8, 9 and 10 - - 0. 5 v input leakage current ilh vin=vdd, pins 5, 6 and 7 -35 - 35 a input leakage current ill vin=gnd, pins 5, 6 and 7 -2 0 - 2 0 a pull -do wn resistor rp d pins 5, 6 and 7 100 150 250 k operating supply current idd1 clkin=26mhz, oe1=oe2=oe3=1 - 3. 4 - ma operating supply current idd2 oe1=oe2=oe3=0 clkin=low or high - - 2 .0 a input capacitance cin pins 5, 6 and 7 - 3 5 pf load capacitance cl clkout 1/2/3, pins 8, 9 and 10 - 10 2 5 pf
rev 1.8, march 16 , 2012 page 3 of 12 SL18860DC ac electrical characteristics (i - grade) unless otherwise st ated vdd= 3.3v+/ - 10% and operation temperature range - 40 to +85c parameter symbol condition min typ max unit input clock range clkin external clock, cmos square wave 10 26.000 52 mhz output clock range clkout external clock, cmos square wave clkout1/2/3 10 26.000 52 mhz input clock voltage swing level vinpp vdd=3.3v , connect to clkin directly 1.32 1.4 - v vdd=3.3v, connect to clkin through ac coupling and bias circuit 0.6 - - v input duty cycle dcin clkin, pin 3 30 50 70 % output clock rise time tr vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 1.2 2.2 ns output clock fall time tf vdd=1.8, cl=10pf, measured from 10 to 90% of vdd , pins 4, 8, 9 and 10 - 1.2 2.2 ns additive phase noise apn -1 clkin=26mhz and 1 khz offset clkout1/2/3 - -138 - dbc/hz additive phase noise apn -2 clkin=26mhz and 10 khz offset clkout1/2/3 - -1 57 - dbc/hz additive phase noise apn -3 clkin=26mhz and 100 khz offset clkout1/2/3 - -165 - dbc/hz power - up time tpu time duration until clkout1/2/3 fr equency reaches valid frequency after power supply reaches 0.9xvdd value - 100 200 n s output enable time toe1 time from oe raising edge to active at outputs clkout1/2/3 (asynchronous) - 2 5 - n s output disable time tod time from oe falling edge to hi - z at outputs clkout1/2/3 (asynchronous) - 25 - n s output enable time toe2 active recovery time from standby (clkin=0 or 1) to active at outputs clkout1/2/3 - 100 - n s
rev 1.8, march 16 , 2012 page 4 of 12 SL18860DC SL18860DC clkout1/2/3 phase noise (dbc/hz) cl=15pf. vdd(v) 100hz 1khz 10khz 100khz 1mhz 5mhz fig # 1.8 -115.52 -139.85 -150.79 -159.31 -160.52 -162.52 1 2.5 - 125.16 - 142.67 - 156.37 - 164.02 - 166.45 - 167.02 2 3.3 - 116.60 - 138.06 157.41 - 164.88 - 167.21 - 168.57 3 table 2. output phase noise summary table figure 1. output phase noise vdd=1.8v, cl=15pf
rev 1.8, march 16 , 2012 page 5 of 12 SL18860DC figure 2 . output phase noise vdd=2.5 v, cl=15pf figure 3 . output phase noise vdd=3.3 v, cl=15pf
rev 1.8, march 16 , 2012 page 6 of 12 SL18860DC typical application circuit vss 1 c2 (0.1 f) c1 (10f) r1 (50) vdd=1.8v to 3.3v clkin 3 6 7 5 oe1 oe2 oe3 8 9 10 clkout1 clkout3 clkout2 oe_osc 4 SL18860DC (26.000mhz-typ) (26.000mhz-typ) (26.000mhz-typ) (26.000mhz-typ) 2 ac coupling and bias circuit tcxo vdd sl18860 vcc r r2 c1 22nf
rev 1.8, march 16 , 2012 page 7 of 12 SL18860DC package outline and package dimensions 10- pin tdfn package (1.4x2.0x0.75 mm ) top view bottom view side view side view
rev 1.8, march 16 , 2012 page 8 of 12 SL18860DC ordering inf ormation order ing number marking shipping package package temperature sl 18860dc 860 tube 10- pin tdfn -40 to 85c sl 18860dct 860 tape and reel 10- pin tdfn - 40 to 85c note : the sl18860 is rohs compliant marking diagram : 860 yww pin 1 yww: y = last digit of year ww = work week the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any co nsequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without furthe r notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or c ircuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized app lication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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